1. Field of the Invention
Example embodiments of the present invention relate generally to a probe card, an apparatus and a method for inspecting an object, and more particularly to a probe card, an apparatus and a method for inspecting an object including normal or abnormal chips.
2. Description of the Related Art
A conventional semiconductor device manufacturing process may include forming a pattern on a semiconductor substrate and dividing the semiconductor substrate into a plurality of chips based on the pattern. An electrical die sorting (EDS) process for inspecting electrical characteristics of each of the plurality of chips may be carried out between the formation of the pattern and the dividing of the substrate into the plurality of chips.
Abnormal chips among the plurality of chips may be detected by the EDS process. In an example, a probe card may be used in the EDS process. The probe card may supply an inspection current to each of the plurality of chips. The probe card may determine whether or not each of the plurality of chips is normal based on an electrical signal outputted from the chips in response to the supplied inspection current. A conventional probe card may include a printed circuit board (PCB) upon which electrical circuits may be formed, and also a plurality of needles for making contact with the electrical circuits to provide the chips with the inspection current.
A conventional exposure process for forming a pattern may be performed on a single region of a semiconductor substrate upon which only one chip may be formed. Alternatively, the exposure process may be executed simultaneously at two regions of a semiconductor substrate in order to improve an efficiency of a semiconductor manufacturing process as compared to the single-chip exposure process.
An “abnormal” chip may be formed on an edge portion of the semiconductor substrate, or, alternatively, on a central portion of the semiconductor substrate surrounded by the edge portion. In an example, the abnormal chip may include an abnormal circuit, such as a short circuit or an opened circuit.
FIG. 1 is a cross-sectional view illustrating a conventional probe apparatus 10 for inspecting electrical characteristics of a semiconductor substrate. Referring to FIG. 1, the conventional probe apparatus 10 may include an inspection unit 20, a probe card 30 and a current cutting unit 40. The probe card 30 may include a PCB 31 upon which circuits 32 may be formed, and a plurality of needles 35 may be electrically connected to the circuits 32 one by one. The inspection unit 20 may supply inspection currents to each of the circuits 32. The needles 35 may make contact with a plurality of chips to provide the chips with the inspection currents.
Referring to FIG. 1, when the inspection current is supplied to an abnormal chip C2 through the needle 35, an excessive current may be applied to the needle 35 from the abnormal chip C2. Because a relatively high amount of heat may be generated at a tip of the needle 35 to which the excessive current may be applied, the tip of the needle 35 may be burnt out such that the needle 35 may not be usable. In order to reduce the occurrence of the needle 35 being “burnt out”, the current cutting unit 40 may cut off the supply of the inspection current to the needle 35.
While the conventional probe apparatus 10 shown in FIG. 1 may reduce the occurrence of tips of the needle 35 being “burnt out”, the probe apparatus 10 may be associated with a relatively complex circuit arrangement of the circuits 32 in the PCB 31 and also may reduce the efficiency of the inspection because the inspection currents may be separately supplied to each of the needles 35.
FIG. 2 is a cross-sectional view illustrating another conventional probe apparatus 50 for inspecting electrical characteristics of a semiconductor substrate
Referring to FIG. 2, the conventional probe apparatus 50 may include an inspection unit 60, a probe card 70 and a current cutting unit 80. The probe card 70 may include a PCB 71 upon which circuits 72 may be formed, and may further include a plurality of needles 75 electrically connected to the circuits 72. The needles 75 and the circuits 72 may have a plural-to-one correspondence (e.g. twice the number of needles 75 to circuits 72). For example, one (1) circuit 72 may be electrically connected to two (2) needles 75. Thus, a single inspection current from the circuit 72 may be halved. The halved inspection currents may then be supplied to each of the two needles 75, respectively.
Therefore, the number of the circuits 72 in the probe apparatus 50 of FIG. 2 may be half that of the circuits 32 in the probe apparatus 10 of FIG. 1. Further, the probe apparatus 50 of FIG. 2 may have an improved inspection efficiency compared to that of the probe apparatus 10 of FIG. 1.
However, when the two needles 75 receiving the inspection currents from the circuit 72 simultaneously make contact with a normal chip C1 and an abnormal chip C2, respectively, the current cutting unit 80 may not block the supply of the inspection current supply into the two needles 75. When the current cutting unit 80 blocks (i.e., cuts off) the inspection current supply, the inspection currents may not flow into the needle 75 making contact with the normal chip C1 and/or the needle 75 connected to the abnormal chip C2 such that an inspection of the normal chip C1 may not be performed. To perform the inspection with respect to the normal chip C1, the supply of the halved inspection current into the abnormal chip C2 may be neglected. As a result, the inspection currents may flow into the tip of the needle 75 making contact with the abnormal chip C2, hence the tip of the needle 75 may still become burnt out.